| Research Title |
Transforming of the Sequence Diagram into
Time-Automata Network |
| Date of Distribution |
7 July 2023 |
| Conference |
| Title of the Conference |
The 29th International MultiConference of Engineers and Computer Scientists (IMECS 2023) |
| Organiser |
International Association of Engineers (IAENG) |
| Conference Place |
Hong Kong |
| Province/State |
|
| Conference Date |
5 July 2023 |
| To |
7 July 2023 |
| Proceeding Paper |
| Volume |
2023 |
| Issue |
1 |
| Page |
147-152 |
| Editors/edition/publisher |
|
| Abstract |
Formal verification using a model checking
approach is a process for proving undesirable properties in
designed models. The model checking procedure for the
sequence diagram is cumbersome because the transformation of
the sequence diagram into a formal model requires meticulous
mapping rules and methods that must yield corresponding
behaviors. This paper proposes the transformation of the
sequence diagram into a time automate named UPPAAL. The
obtained time automata model can be used to verify deadlock,
undesirable properties, and the correctness of message ordering.
The transformation rules and framework were experimented
with case studies. The results show that the proposed
transformation rules can be applied and map the sequence
diagram into a UPPAL structure correctly. |
| Author |
|
| Peer Review Status |
มีผู้ประเมินอิสระ |
| Level of Conference |
นานาชาติ |
| Type of Proceeding |
Full paper |
| Type of Presentation |
Oral |
| Part of thesis |
true |
| ใช้สำหรับสำเร็จการศึกษา |
ไม่เป็น |
| Presentation awarding |
false |
| Attach file |
|
| Citation |
0
|
|
|
Publication
Journal Publication
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